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设计一个7.5分频的分频器，不能使用PLL

法一

author : Mr.Maoe-mail : 2458682080@qq.commodule Fre_div_decimal(clk, rst, div_out, count, clkN, clkP);  input clk, rst ;    output div_out, clkN, clkP ;    output [4:0] count ;		  reg [4:0] count;    wire [4:0] shift_count; //移位计数    reg clkP,clkN;  assign shift_count = 5'b00001;  always @ (posedge clk or negedge rst)  begin  			if(!rst)  count <= shift_count ;							else      count <= {count[3:0], count[4]} ;  //实现移位计数（左移）00001》00010》00100》01000》10000》00001					  end      always @ (negedge clk or negedge rst)  begin  		  if(!rst)                                           clkN <= 1'b0 ;						  else if(count == 5'b01000 || count == 5'b10000)    clkN <= 1'b1 ;				 		  else                                               clkN <= 1'b0 ;    end      always @ (posedge clk or negedge rst)  begin  			if(!rst)                                          clkP <= 1'b0 ;							else if(count == 5'b00001 || count == 5'b00010)   clkP <= 1'b1 ;				 			else                                              clkP <= 1'b0 ;    end  assign div_out = clkP | clkN ;endmodule

法二

author : Mr.Maoe-mail : 2458682080@qq.commodule div7p5x(	input clk,	input reset_n,	output q);reg [3:0] cnt;reg x_p,x_n;always @(posedge clk,negedge reset_n)	if(!reset_n)		cnt <= 0;	else if(cnt < 15-1)		cnt <= cnt + 1'b1;	else		cnt <= 0;always @(posedge clk,negedge reset_n)			if(!reset_n)				x_p <= 0;			else  if(cnt < 15/4)				x_p <= 1;			else				x_p <= 0;always @(negedge clk,negedge reset_n)					if(!reset_n)						x_n <= 0;					else if(cnt > 15/2 && cnt <= 15/2+15/4)						x_n <= 1;					else						x_n <= 0;						assign q = x_p | x_n;													endmodule

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